I had the fantastic opportunity to speak at Cosyne 2026, in the workshop on Biologically-Inspired Artificial Intelligence. Cosyne is one of the leading conferences in (computational) neuroscience, and it was my first time attending it. The community is creative, welcoming, and genuinely curious about the deep questions at the intersection of biology and computation. Being an engineer surrounded by computational neuroscientists for a few days was truly inspiring.

What Role Does Neuroscience Play in the Age of AI?

It is hard to ignore that AI is advancing at a pace that would have seemed implausible just a few years ago. Large language models are reshaping the concept of intelligence and, notably, do not look much like brains. Backpropagation through deep networks, attention mechanisms, and massive parallelism on GPU clusters are a long way from local plasticity, spike-timing-dependent learning, and the roughly 20 watts of power consumed by the human brain.

So what role does neuroscience play in this context? Is biological inspiration still a useful guide for building intelligent systems, or has it become more of an aesthetic preference?

As a neuromorphic engineer, I feel this growing tension. Neuromorphic computing has historically drawn deep inspiration from biology, often at the level of mimicking individual neurons and synapses. But as the gap between neuromorphic hardware and state-of-the-art AI grows wider, it becomes worth asking: are we drawing the right kind of inspiration?

Three Levels of Biological Inspiration

I find it useful to distinguish between three levels, which map onto different parts of the stack of engineering intelligence — from devices and circuits all the way up to applications and algorithms.

Courtesy of Melika Payvand.

1. Mechanical Level

The mechanical level is about faithfully mimicking the biophysics of neural computation: the dynamics of individual neurons, synapses, axons, and dendrites. This is where traditional neuromorphic engineering has lived, designing circuits that reproduce the biophysical dynamics of real neurons, memristive devices that implement synaptic plasticity, or architectures that implement dendritic compartments.

The mechanical level asks: what of the complex neuronal biophysics is useful for computation and how?

2. System Level

The system level takes a step up, adopting the “mechanisms” of machine learning — artificial neural networks and backpropagation — but inject biological system-level features: heterogeneity across neurons, functional specialization of different brain areas, sparse connectivity, modularity, or principles like neurogenesis. It’s not trying to replicate the biophysics, it’s rather making the hypothesis that the organisational principles of biological neural systems can make artificial ones better.

The system level asks: can biological organizational principles improve the function of artificial networks?

3. Behavioral Level

The behavioral level draws inspiration from how brains act, rather than how they are built. This is closest to classical AI: designing systems that exhibit intelligent behaviors such as perception, decision-making, and creativity, observed in animals, without necessarily caring about the underlying substrate.

Notably, this level is as much about sensing as it is about computation: behavior, after all, emerges from the interaction with an environment. This makes behavioral inspiration particularly relevant for embodied AI, though not exclusively: systems like large language models draw on behavioral inspiration while operating purely in the symbolic domain.

Where Neuromorphic and NeuroAI Currently Live

Neuromorphic engineering has traditionally operated at the mechanical level, while NeuroAI has worked mainly between the system and behavioral levels. But I believe both fields have much to gain from moving across this hierarchy, forming a synergy.

This is also the direction my lab — the Emergent Intelligent Substrates (EIS) Lab, led by Prof. Melika Payvand — has been pursuing.

What We Work On

Let me show you what this looks like in practice across two of these levels.

Mechanical Level: Dendritic Delays

Dendrites exhibit a rich repertoire of computational primitives, one of which is the propagation delay of pre-synaptic stimuli as they travel toward the soma. This delay is a form of temporal memory built directly into the morphology of the neuron.

DenRAM mimics dendritic arbors with synaptic elements that delay and weigh input spikes, converging to an output Leaky-Integrate-and-Fire neuron.

In DenRAM (D’Agostino, Moro et al., Nature Communications 2024), we built a neuromorphic hardware architecture that uses Resistive RAM (RRAM) to implement dendritic delays with ultra-low power consumption. Delay-based spiking networks turn out to be significantly more efficient than recurrent models: we demonstrated a 5× reduction in power and up to a 35× reduction in memory footprint on ECG anomaly detection and keyword spotting benchmarks.

One limitation of DenRAM is that it does not train the delays explicitly. This motivated DelGrad (Göltz, Weber, Kriener et al., Nature Communications 2025), an algorithm that derives exact, event-based gradients for both synaptic weights and delays in spiking networks. DelGrad is compatible with LIF neurons and has been validated on neuromorphic hardware (BrainScaleS), where training axonal delays reduces test error meaningfully even under the noise of analog hardware.

Together, DenRAM and DelGrad make the case that the mechanical richness of dendrites — specifically, their temporal structure — is a powerful computational resource.

System Level: Heterogeneous Memory, Temporal Hierarchy, and Neurogenesis

Moving up the hierarchy, we have been working on how biological system-level principles can improve artificial networks trained with backpropagation.

In the system-level of biological inspiration, we leverage machine-learning computational mechanisms in conjunction with high-level features of biological computations.

mGRADE (Torchet et al., arXiv 2025) combines two ideas: the minimal gated recurrent unit (minGRU) for processing slow temporal dynamics, and dilated convolutions with learnable spacings (DCLS) for capturing fast temporal features. The result is a deep recurrent network with heterogeneous memory — inspired by the fact that brains exhibit heterogeneous strategies for memory formation. mGRADE achieves state-of-the-art performance on the Long Range Arena benchmark and on raw-audio keyword spotting, while being the only architecture in its class small enough to fit on common microcontrollers.

Temporal Hierarchy in SNNs (Moro et al., arXiv 2024) investigates whether the hierarchy of intrinsic timescales observed in the mammalian cortex — where deeper cortical areas process information over longer timescales — is also useful as an inductive bias in artificial spiking networks. The answer is yes: imposing a structured gradient of time constants across hidden layers consistently improves performance on temporal tasks, and interestingly, this hierarchy also emerges spontaneously from optimization when networks are trained on sequential data.

GroHess takes inspiration from adult hippocampal neurogenesis — the brain’s ability to grow new neurons as a mechanism for continual learning — and implements a biologically-motivated artificial counterpart. Using information-geometry-based triggers (effective dimensionality and Fisher saturation metrics), the algorithm decides when and where to grow new neurons, and initialises them orthogonally to the existing representations to minimise interference. On both Split MNIST and Permuted MNIST, GroHess achieves better performance with smaller final models than static baselines.

Looking Ahead: A Synergy Worth Pursuing

I believe the future of both fields lies in their convergence.

NeuroAI would benefit from engaging more seriously with neuromorphic hardware. Energy-efficient substrates impose structure that may turn out to be a feature rather than a limitation: sparse connectivity, modular networks and local learning rules are all biologically motivated and increasingly attractive from an engineering standpoint.

Neuromorphic engineering should break free from its focus on the mechanical level. The most impactful near-term opportunities may lie in the system level: using the organizational principles of biological brains — hierarchy of time-scales, heterogeneous dynamics, modular connectivity — to build systems that are simultaneously more efficient and more functional.

The next step is to build systems that are neuromorphic in substrate, biologically-organized at the system-level, while leveraging the powerful computational tools of machine learning. I think we are closer to that than it might seem.

Filippo Moro is a Postdoc in the EIS Lab at UZH and ETH Zurich, led by Prof. Melika Payvand. His research sits at the intersection of neuromorphic hardware, spiking neural networks, and biologically-inspired machine learning.

Here I explore the current on-chip memory landscape to extrapolate what the future might look like. More importantly, this article links to a spreadsheet where I gather data on all the memory devices featured in the plots. You can access this spreadsheet freely and will find all the information about the given memory devices, as well as a reference to the scientific paper in which they were featured.

Memory is all you need

Memory technology has become the major battleground for integrated chip innovation. Our chips’ integrated memory is ever-growing and now occupies a considerable portion of commercial silicon dies. While Static-Random-Access-Memory technology dominates the on-chip memory market, an article pointed out that SRAM’s scaling - fueled so far by Moore’s Law - is hitting a wall [1]. TSMC’s 3nm node only provides a minor improvement (about 5%) in SRAM bitcell density compared to the 5nm node. So what is the future for on-chip memory?

Some suggest that the shift from FinFET to Nanosheet transistor technology will propel the continuation of CMOS - and SRAM as well - scaling. Others highlight that alternative solutions exist: several emerging memory cells have been developed with the aim of going beyond standard CMOS and exploiting different physical phenomena to store information in memory cells. Among such innovative devices are Resistive-RAM (RRAMs) [2], Phase-Change-Memory (PCM) [3], Magnetic-RAM (MRAM) [4], Ferroelectric-RAM (FeRAM) [5], 2T-Gain-Cells [6], and eDRAM [7]. Although far less mature than SRAM, these devices (except for 2T-Gain-Cells and eDRAM) are non-volatile, thus promising energy efficiency, and can easily be integrated into the Back-End-of-Line (BEOL) of common CMOS processes, enabling high memory integration density.

This article offers a bird’s-eye view of the memory technology landscape, analyzing SRAM development down to the most recent nodes and assessing the performance of alternative emerging memory devices. Importantly, this article is inspired by this excellent review paper from Prof. Shimeng Yu. I build on top of this article by finding relevant sources in the literature and providing my own opinions on the future of memory technology. You can access all the information contained in this article from this spreadsheet: it features scientific references and technical information on many memory devices.

SRAM scaling

Pushed by advances in transistor technology, SRAM performance has improved at an astounding pace over the years. Here we focus on SRAM scaling after the year 2000, showing the impressive rate at which cell size has shrunk.

Scroll through the 3 figures!

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This data, again, is reported in the shared spreadsheet and from it we can learn three main messages:

• 1: SRAM bit-cell size has steadily decreased through the years, but it appears to have slowed down lately.
• 2: planar CMOS technology hit a wall at the beginning of the 2010s, when FinFET technology took over and continued the scaling trend.
• 3: only three companies are currently participating in the race of SRAM scaling (TSMC, Samsung, Intel).

As technology nodes become more advanced, the investments required to participate in the silicon scaling race grow exponentially. This is why the leading edge of SRAM scaling is carried out by essentially only one company nowadays, TSMC. Samsung follows closely, and Intel seems to be lagging a little behind.

Will SRAM scaling continue?

It seems like SRAM scaling is becoming harder and harder, and even TSMC flinched when launching its 3nm node, with the N3B specification offering only a 5% improvement over the N5 (5nm) node [1]. However, the semiconductor industry still has some tricks up its sleeves, and it is ready to play them all to ensure the continuation of SRAM scaling.

• Nanosheet transistors: the next generation of transistors promises higher integration density, guaranteeing the continuation of SRAM scaling.
• Backside power rails: an option mainly researched by Intel.
• Forksheet transistor: a development of Gate-All-Around transistors enabling greater transistor density.
• Complementary 3D stacked logics: a potentially disruptive technology whereby p- and n-mos transistors can be stacked on top of each other, offering clear scaling advantages even compared to ultimate nanosheet transistors.

Alternative emerging memory technology

Embedded Non-Volatile Memory (eNVM)

As advanced technology nodes become ever more expensive and technically challenging, very few companies can afford to continue CMOS development. This leads researchers to explore novel memory devices that operate by exploiting different physical phenomena. This class of emerging memories has been discussed a lot, so how does it compare with SRAM? We’ll now focus on emerging non-volatile memory (eNVM), which includes RRAM, MRAM, PCM, and FeRAM. (The latter is not mature enough to be compared in the following plots.)

Scroll through the 2 figures!

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This data, once more, is reported in the shared spreadsheet:

• 1: in terms of bit-cell size, eNVM is competitive with SRAM, especially RRAM and PCM.
• 2: however, memory array density highlights that eNVM is, for now, reserved for larger technology nodes (typically 40nm or 28nm, topping at 14nm), and thus eNVM is currently less memory-dense.

For now we have mainly looked at size and density, but there is more to memory. The next figure gives an idea of the figures of merit of different memory technologies, comparing SRAM (in gray) to eNVM. Note that this figure is obtained by considering the general performance of the different memory classes, taking inspiration from Table 1 in [8].

What do we learn? SRAM and eNVM are apples and oranges. They do not belong to the same class of memory devices, which are famously clustered in the memory pyramid (refer to Figure 2 in [8]). In particular, the core differences are:

• SRAM is fast! eNVM is slower to read and even slower to write.
• SRAM has extremely high endurance (number of read/write cycles before failure). MRAM also features high endurance, but RRAM and PCM are very limited in this sense.
• Despite SRAM being the densest so far, RRAM and PCM feature multi-bit per cell. The density gap might close in the future!

The future of memory technology

(What follows is my personal opinion)

It is hard to predict what the future of memory technology will look like. My opinion is that until transistor scaling will be physically possible and economically viable, industry will keep developing in that direction, bringing benefits to SRAM scaling. Concerning memory applications, it’s hard to see SRAM dethroned as L1 and L2 cache memory, where sheer speed is mandatory. There is no other device currently capable to deliver similar read and write speed.

However, transistor scaling will likely hit a point of diminishing returns at some point. Are the alternative memory devices ready to take over when this happens? Again, it depends on the applications.

• eNVM is already in the market, as embedded memory in commercial micro-controllers [9].
• As L3 or L4 cache memory, MRAM might evolve into a serious candidate, especially when its non-volatility can be exploited in low stand-by power contexts.

Compute-In-Memory

The most intriguing domain of application for eNVM is certainly Compute-in-Memory (CIM). While SRAM-based CIM is definitely high-performing, breaking the 1000 Tops/W mark per macro, eNVM-based CIM is also competitive [10]. eNVM features two important characteristics that are still not fully exploited in CIM, especially in low-power applications. While SRAM is the speed king and maximally efficient only at peak frequency, eNVM does not consume any static power (in theory!), and it is thus energy-efficient even at low frequency, a typical use case for edge applications. Also, RRAM and PCM store multiple bits per cell (typically 3 bits): this aspect is rarely exploited as it makes peripheral circuit design more complex (you need to design a compact ADC), but it might give an edge to eNVM in terms of CIM memory density.

Scaling in the third dimension

But there is an important prospect to account for: 3D memory integration [11]. Nowadays, 3D integration is reserved for Flash memory, achieving more than 100 levels in the Back-End-of-Line and thus record-breaking memory density [12]. SRAM is very likely not scalable to 3D, as crystalline silicon cannot be deposited in the BEOL to form the six transistors required by SRAM. In contrast, eNVM is already BEOL-compatible. So can it scale to 3D? Yes, but it will be complicated. Some early research showed BEOL integration of RRAM and a carbon-nanotube selector [13], potentially scalable to multiple 3D layers. This paves the way toward ultra-high on-chip memory density.

Thanks for reading! Please do not hesitate to provide feedback; you can find my contacts on the landing page of my website (provide links!). Also check out the Emerging Intelligent Substrates Lab (EIS), directed by Melika Payvand. It is a cool environment where novel memristive-based architectures and neuromorphic algorithms are co-designed, leading to creative and competitive neuromorphic solutions.

Visit the EIS Lab GitHub.

References

[1] David Schorr “IEDM 2022: Did We Just Witness The Death Of SRAM?” WikiChip Fuse (2022)

[2] Wong, H-S. Philip, et al. “Metal–oxide RRAM.” Proceedings of the IEEE 100.6 (2012): 1951–1970.

[3] Ielmini, Daniele, et al. “Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation.” 2007 IEEE International Electron Devices Meeting. IEEE, 2007.

[4] Na, Taehui, Seung H. Kang, and Seong-Ook Jung. “STT-MRAM sensing: a review.” IEEE Transactions on Circuits and Systems II: Express Briefs 68.1 (2020): 12–18.

[5] Mikolajick, Thomas, et al. “FeRAM technology for high density applications.” Microelectronics Reliability 41.7 (2001): 947–950.

[6] Liu, Shuhan, et al. “Hybrid 2T nMOS/pMOS Gain Cell Memory with Indium-tin-oxide and Carbon Nanotube MOSFETs for Counteracting Capacitive Coupling.” IEEE Electron Device Letters (2023).

[7] Fredeman, Gregory, et al. “A 14 nm 1.1 Mb embedded DRAM macro with 1 ns access.” IEEE Journal of Solid-State Circuits 51.1 (2015): 230-239.

[7] Dalgaty, Thomas, et al. “In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling.” Nature Electronics 4.2 (2021): 151–161.

[8] Mannocci, P., et al. “In-memory computing with emerging memory devices: Status and outlook.” APL Machine Learning 1.1 (2023).

[9] STMicroelectronics, announcing an 18nm FD-SOI platform with ePCM.

[10] Shanbhag, Naresh R., and Saion K. Roy. “Comprehending in-memory computing trends via proper benchmarking.” 2022 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2022.

[11] Vianello, Elisa, and Melika Payvand. “Scaling neuromorphic systems with 3D technologies.” Nature Electronics 7.6 (2024): 419-421.

[12] Kim, Bvunarvul, et al. “28.2 A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers” 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2023.

[13] Srimani, Tathagata, et al. “Foundry monolithic 3D BEOL transistor+ memory stack: Iso-performance and Iso-footprint BEOL carbon nanotube FET+ RRAM vs. FEOL silicon FET+ RRAM.” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits). IEEE, 2023.

If you’re here, you probably already know what memristors are, but in case you don’t: memristors are a novel class of electronic devices that exhibit interesting properties, including the ability to assume different resistance levels and hold their resistive state without requiring static power consumption. In a nutshell, they are non-volatile memories. Memristors can be made of different materials and, according to the physical principle they exploit, they are classified into the following main categories: Resistive-Random-Access-Memories (RRAMs) [1,2], Ferroelectric-RAMs (FeRAMs) [3,4], Phase-Change-Memories (PCMs) [5], and Magnetic-RAM (MRAM) [6].

Different types of memristors: RRAMs feature a conductive resistive filament, FeRAMs multiple ferroelectric domains, PCM phase change materials, MRAMs magnetic domains.

Are memristors any good?

Yes, definitely! For the following reasons:

• Small cell size → high integration density
• Multi-level states* → high memory density
• Non-volatility → (virtually) zero static power consumption

*except for MRAMs, which are binary devices

In particular, memristors can be arranged in arrays and enable efficient in-memory matrix-vector multiplication (MVM). Weights from a matrix W can be mapped onto the conductances G in the memristive array, and the inputs X are presented as voltages V at the rows of the array. Exploiting Ohm’s and Kirchhoff’s laws, the currents at the columns, I, compute the MVM output Y = WX. If you know anything about neural networks, you’ll be aware that MVM operations are at the very core of neural-network computation. That’s where all the hype around memristive systems for artificial intelligence stems from.

Efficient implementation of the Matrix-Vector-Multiplication (MVM) with a memristive array (right). Each weight in matrix W can be mapped to a conductance G in the memristive array.

Is there a catch with memristors?

Well, yes, memristors also have their issues.

The main issue with memristors is their variability. What does it mean? Imagine you have 100 memristors, you program them with the same programming conditions, and then you look at their state. You will observe a distribution of resistance levels due to so-called ‘device-to-device’ variability. Furthermore, if you program the same device 100 times, you will also observe a distribution of resistances due to ‘cycle-to-cycle’ variability. If you measure the state of a memristor over time, you might see its resistive level oscillate or even drift due to ‘read-to-read’ noise, ‘random-telegraph-noise’, and potentially even ‘thermal-drift’. Long story short, memristors suffer from variability and noise, which make it hard to precisely control their resistance. Although neural networks can tolerate slight imprecision in their weights, the amount of variability introduced by memristors generally disrupts neural-network performance.

Notice that the variability in RRAMs is in the [5–15]% interval, considering the mean resistance over the standard deviation. Other memristive technologies report similar levels of variability.

Example of variability in RRAM devices. a) RRAM device-to-device variability after programming 4096 devices with the same programming conditions. HCS stands for High-Conductive-State. b) Measurement of cycle-to-cycle variability. The "Current" x-axis refers to the programming condition. From [7].

Is there a fix for memristors’ variability?

Yes, in the form of Memristive-Aware-Training! :)

The trick is to introduce device noise during training, so that the network gets used to memristor variability. Practically, such a training scheme aims to avoid narrow valleys in the loss function and find a flatter local minimum, where perturbations due to memristor variability create fewer problems. How can you introduce noise during training? With the Straight-Through-Estimator function. It’s a common technique for training quantized/binarized neural networks, and it consists of decoupling the weight matrices used for the forward and backward passes. In this way, one can use noisy memristive weights for inference and perform weight updates on the original unperturbed weights. To do this, all it takes is a simple function added to the forward pass of your neural network model. In PyTorch, this can be implemented as follows:

# STE function to apply noise in the forward pass
class Noisy_Inference(torch.autograd.Function):
    """
    Function taking the weight tensor as input and applying gaussian noise with standard deviation 
    (noise_sd) and outputting the noisy version for the forward pass, but keeping track of the 
    original de-noised version of the weight for the backward pass
    """
    noise_sd = 1e-1

    @staticmethod
    def forward(ctx, input):
        """
        In the forward pass we add some noise from a gaussian distribution
        """
        ctx.save_for_backward( input )
        weight = input.clone()
        # registering the span of weight values
        delta_w = 2*torch.abs( weight ).max()
        # noise tensor to be applied to the weights
        noise = torch.randn_like( weight )*( Noisy_Inference.noise_sd * delta_w )
        return torch.add( weight, noise )

    @staticmethod
    def backward(ctx, grad_output):
        """
        In the backward pass we simply copy the gradient from upward in the computational graph
        """
        input, = ctx.saved_tensors
        weight = input.clone()
        return grad_output
noiser = Noisy_Inference.apply

# Application of the STE to a linear layer
# out_noisy = torch.nn.functional.linear( input, noiser(weight), noiser(bias) )

Does Memristor-Aware-Training work? Yes, it does! Look at the results.

As discussed, Memristor-Aware-Training (MAT) helps neural networks find a weight configuration that is resilient to perturbation. It’s very similar to the Quantization-Aware-Training technique [8], where model parameters are quantized during training to mitigate performance loss due to weight quantization for deployment on resource-constrained hardware (limited bit precision). In the same way, MAT makes the network resilient to memristor noise and variability. Check out the effect of MAT on the very common MNIST handwritten-digit recognition task under different weight-perturbation levels. In the example below, weights are perturbed both during training and during testing with Gaussian distributions whose standard deviation is normalized by the maximum weight magnitude (and reported as a percentage). The training noise standard deviation is 20%.

Accuracy of a Multi-Layer Perceptron (size of 728–128–10) on MNIST under different weight perturbation magnitudes during Inference. Reference is trained without the noise injection, while MAT is trained with 20% noise injection.

So how does MAT work?

It’s really simple: all it takes is following these steps:

• Pre-training without noise
• Activating the noise injection function on your model
• (Re-)Training with noise injection
• Deployment on memristive hardware :)

This exact methodology has been adopted for very successful early implementations of Deep Neural Networks on memristive substrates, resulting in high-impact factor journal publications:

→ NeuRRAM [9]: an RRAM-based accelerator demonstrated with a ResNet-20 on CIFAR10, with >88% accuracy on-chip. → Joshi, Vinay, et al. “Accurate deep neural network inference using computational phase-change memory.” Nature Communications 11.1 (2020): 2473. [10], where a ResNet-32 reaches 71.6% accuracy on ImageNet.

With a similar methodology, MAT is demonstrated in simulation with a MobileNet-V2 network on the CIFAR-10/100 tasks, with the following results.

Notably, the technique described above is not the only one proven successful for deploying neural networks on memristive substrates. A solution is proposed in [11], accounting for memristive non-linearity in the training phase, while [12] introduces noise during training with Bayesian-optimized dropout layers. Possibly, these techniques could be complementary and might even be combined with Memristor-Aware-Training to yield better results. This post aims to spread knowledge about the Memristor-Aware-Training technique and promote the development of memristive systems for artificial intelligence, which have strong potential to become a disruptive technology for edge-AI applications. For this reason, the code to obtain the results shown in this post is shared on the following GitHub page, belonging to the EIS group.

Visit the Memristor-Aware-Training GitHub repo.

Also check out the Emerging Intelligent Substrates Lab (EIS), directed by Melika Payvand. It’s a cool environment where novel memristive-based architectures and neuromorphic algorithms are co-designed, leading to creative and competitive neuromorphic solutions.

Visit the EIS Lab GitHub.

References

[1] Wong, H-S. Philip, et al. “Metal–oxide RRAM.” Proceedings of the IEEE 100.6 (2012): 1951–1970.

[2] Kim, M. J., et al. “Low power operating bipolar TMO ReRAM for sub 10 nm era.” 2010 International Electron Devices Meeting. IEEE, 2010.

[3] Mikolajick, Thomas, et al. “FeRAM technology for high density applications.” Microelectronics Reliability 41.7 (2001): 947–950.

[4] L. Grenouillet et al. “Performance assessment of BEOL-integrated HfO 2-based ferroelectric capacitors for FeRAM memory arrays”. In: 2020 IEEE Silicon Nanoelectronics Workshop (SNW). IEEE. 2020, pp. 5–6.

[5] Ielmini, Daniele, et al. “Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation.” 2007 IEEE International Electron Devices Meeting. IEEE, 2007.

[6] Na, Taehui, Seung H. Kang, and Seong-Ook Jung. “STT-MRAM sensing: a review.” IEEE Transactions on Circuits and Systems II: Express Briefs 68.1 (2020): 12–18.

[7] Dalgaty, Thomas, et al. “In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling.” Nature Electronics 4.2 (2021): 151–161.

[8] Jacob, Benoit, et al. “Quantization and training of neural networks for efficient integer-arithmetic-only inference.” Proceedings of the IEEE conference on computer vision and pattern recognition. 2018.

[9] Wan, Weier, et al. “A compute-in-memory chip based on resistive random-access memory.” Nature 608.7923 (2022): 504–512.

[10] Joshi, Vinay, et al. “Accurate deep neural network inference using computational phase-change memory.” Nature Communications 11.1 (2020): 2473.

[11] Joksas, Dovydas, et al. “Nonideality‐Aware Training for Accurate and Robust Low‐Power Memristive Neural Networks.” Advanced Science 9.17 (2022): 2105784.

[12] Ye, Nanyang, et al. “Improving the robustness of analog deep neural networks through a Bayes-optimized noise injection approach.” Communications Engineering 2.1 (2023): 25.